| Acronyms |
Domain |
Description |
|
| ASIC |
IC Designs |
Application Specific Integrated Circuit |
|
| SOC |
IC Designs |
System on Chip |
|
| IP |
IC Designs |
Intellectual Property |
|
| P&R |
Tool |
Place & Route |
|
| HDL |
Design Data |
Hardware Descriptor Language |
|
| DEF |
P&R |
Design Exchange Format |
|
| LEF |
P&R |
Library Exchange Format |
|
| PDEF |
P&R |
Physical Design Exchange Format |
|
| DRC |
Layout Verification |
Design Rule Check |
|
| LVS |
Layout Verification |
Layout v/s Schematic |
|
| ERC |
Layout Verification |
Electric Rule Check |
|
| GDS |
Layout |
Graphic Design System |
|
| CIF |
Layout |
Caltech Intermediate Format |
|
| VHDL |
Layout Verification |
Hardware Definition Language |
|
| EDIF |
Layout Verification |
Electronic Description Information Format |
|
| AMS |
Layout Verification |
Analog Mixed Signal |
|
| MPW |
Layout Verification |
Multi-Project Wafer |
|
| SPF |
Parasitics |
Standard Parastic Format |
|
| DSPF |
Parasitics |
Detailed Standard Parastic Format |
|
| RSPF |
Parasitics |
Reduced Standard Parastic Format |
|
| SPEF |
Parasitics |
Standard Parastic Exchange Format |
|
| DFT |
IC Test |
Design For Test |
|
| JTAG |
IC Test |
Joint Test Action Group |
|
| ATPG |
IC Test |
Automatic Test-Pattern Generation |
|
| ATE |
IC Test |
Automatic Test Equipment |
|
| BIST |
IC Test |
Built-In Self Test |
|
| SDC |
Synthesis |
Synopsys Design Constraints |
|
| SAIF |
Power |
Switching Activity Interchange Format |
|
| Stream |
Design Data |
GDSII Database import and export |
|
| Tape Out |
Foundry Services |
Mask Data ready for delivery to foundry |
|
